The present invention relates to technology for miniaturization of semiconductor integrated circuit devices and more particularly to technology, which is effective for stacked chip semiconductor devices in which two or more semiconductor chips are stacked.
With the recent trend toward smaller and higher-performance electronic systems, demand for smaller and higher-density semiconductor integrated circuit devices is growing. One widely-known technique for increasing the density of a package almost equal in size to a semiconductor chip is a semiconductor device with two or more semiconductor chips stacked which is called a stacked CSP (Chip Size Package).
In this stacked chip semiconductor device, two or more semiconductor chips are stacked in the center of a printed wiring board and a lower semiconductor chip is larger than or equal to an upper one.
When a lower semiconductor chip and an upper one are bonded, an adhesive agent in the form of paste or film is coated over the surface of the lower one, over which the upper one is laid.
Bonding pads are made around peripheral areas of the upper and lower semiconductor chips and electrodes made on the printed wiring board are connected with the bonding pads through bonding wires.
In a stacked CSP memory module in which semiconductor chips including semiconductor memories such as flash memories, DRAMs and SRAMs are stacked, external connection terminals such as address terminals and data input/output terminals (I/O terminals) are shared in order to decrease the number of external connection terminals.
One example of technology for miniaturization of stacked chip semiconductor devices is that a package includes an ESD protection circuit and other buffer circuits such as decoupling capacitors, drivers and receivers which are provided on support chips other than a core integrated circuit chip (for example, see Patent Literature 1: Japanese Unexamined Patent Publication No. Hei 10 (1998)-41458).